Rigorous CMP and electroplating simulations for DFM applications - art. no. 692507

被引：0

作者：

Granik, Yuri ^{[1
]}

Strecker, Norbert ^{[1
]}

机构：

[1] Mentor Graph Corp, San Jose, CA 95131 USA

来源：

DESIGN FOR MANUFACTURABILITY THROUGH DESIGN-PROCESS INTEGRATION II | 2008年 / 6925卷

关键词：

CMP simulation; slurry CMP process; electroplating; chip-scale CMP simulator;

D O I：

10.1117/12.771702

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

We present the chip-scale CMP simulator for layer uniformity analysis within Calibre DFM framework. The CMP simulator is intended to be used during smart fill optimizations, accurate parasitic extractions, defocus variability compensations, and other DFM applications. It is tightly integrated with Mentor Graphics DIM components for yield analysis and optimization. The paper discusses the key concepts of the electro-chemical copper deposition and slurry CMP models that are used in the simulation. The data flow is described, including the use of mask information from design layout data. Application examples, including the process flow and the simulated results, are presented. Both the electroplating and the CMP models include empirical parameters that describe the width- and space- dependency. Fast and accurate global optimization search algorithms are implemented to find optimum modeling parameter values.

引用

页码：92507 / 92507

页数：5

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