BLoG: Post-Silicon Bug Localization in Processors using Bug Localization Graphs

被引：0
|
作者：
Park, Sung-Boem [1 ,2 ]
Bracy, Anne [2 ,3 ]
Wang, Hong [2 ]
Mitra, Subhasish [1 ,4 ]
机构：
[1] Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA
[2] Intel Corp, Microarchitecture Res Lab, Santa Clara, CA USA
[3] Washington Univ, Dept Comp Sci & Engn, St Louis, MO USA
[4] Stanford Univ, Dept Comp Sci, Stanford, CA 94305 USA
来源：
PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE | 2010年
基金：
美国国家科学基金会;
关键词：
Silicon debug; post-silicon validation; IFRA; BLoG; TEST-GENERATION; CHECKING; DEBUG;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Post-silicon bug localization - the process of identifying the location of a detected hardware bug and the cycle(s) during which the bug produces error(s) - is a major bottleneck for complex integrated circuits. Instruction Footprint Recording and Analysis (IFRA) is a promising post-silicon bug localization technique for complex processor cores. However, applying IFRA to new processor microarchitectures can be challenging due to the manual effort required to implement special microarchitecture-dependent analysis techniques for bug localization. This paper presents the Bug Localization Graph (BLoG) framework that enables application of IFRA to new processor microarchitectures with reduced manual effort. Results obtained from an industrial microarchitectural simulator modeling a state-of-the-art complex commercial microarchitecture (Intel Nehalem, the foundation for the Intel Core (TM) i7 and Core (TM) i5 processor families) demonstrate that BLoG-assisted IFRA enables effective and efficient post-silicon bug localization for complex processors with high bug localization accuracy at low cost.
引用
收藏
页码：368 / 373
页数：6
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