A reconfigurable WSI massively data-parallel processing device for cost-effective 3D sensor data processing

被引：0
|
作者：
Lea, RM [1 ]
Tetnowski, PT [1 ]
Covic, M [1 ]
机构：
[1] Brunel Univ, Multimedia Syst & Parallel Comp Technol Res Grp, Uxbridge UB8 3PH, Middx, England
来源：
IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 2000年
关键词：
D O I：
10.1109/DFTVS.2000.887146
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A peformance-scalable ISDP (Interactive Sensor Darn Processing) workstation, accelerated with commercial PCI multiprocessor cards, is described and a WSI Massively data-Parallel Processor (MdPP) device is proposed for the replacement of its VLSI processors. Delivering 60 GOPS for 16-bit integer multipy-accumulate operations, a WSI-FPGA implementation of the reconfigurable device is shown to be better suited to ISDP applications and at least two orders of-magnitude more cost-effective.
引用
收藏
页码：87 / 95
页数：9
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