MRAPI implementation for Heterogeneous Reconfigurable Systems-on-Chip

被引：1

作者：

Gantel, L. ^{[1
,2
]}

Benkhelifa, M. E. A. ^{[2
]}

Verdier, F. ^{[3
]}

Lemonnier, F. ^{[1
]}

机构：

[1] Thales Res & Technol, Embedded Syst Lab, 1 Ave Augustin Fresnel, F-91767 Palaiseau, France

[2] Univ Cergy Pontoise, ENSEA, ETIS Lab, CNRS, F-95014 Cergy Pontoise, France

[3] Univ Nice Sophia Antipolis, CNRS, LEAT Lab, F-06903 Sophia Antipolis, France

来源：

2014 IEEE 22ND ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2014) | 2014年

关键词：

D O I：

10.1109/FCCM.2014.74

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In a Reconfigurable System-on-Chip (SoC) platform, the application is divided into threads managed by an operating system, and whereas some threads are implemented as hardware threads and allocated into a partition of the chip, others run as software threads on embedded processing elements. Relying on the Multicore Resource management API (MRAPI) specification and client-server mechanisms, we propose solutions to provide a flexible access to the operating system services for every threads whatever is the core they are running on. In order to improve the application deployment process when targeting HRSoC, we realized both a hardware and a software implementation of this API. Depending on affinities of the operating system services with each core, such a solution allows a fine-grain implementation of these services over the platform.

引用

页码：239 / 239

页数：1

共 50 条

[1] MRAPI Resource Management Layer on Reconfigurable Systems-on-Chip
Gantel, L.
Benkhelifa, M. E. A.
Verdier, F.
Lemonnier, F.
2014 9TH INTERNATIONAL SYMPOSIUM ON RECONFIGURABLE AND COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC), 2014,
[2] Reconfigurable Convolution Architecture for Heterogeneous Systems-on-Chip
Spagnolo, Fanny
Perri, Stefania
Frustaci, Fabio
Corsonello, Pasquale
2020 9TH MEDITERRANEAN CONFERENCE ON EMBEDDED COMPUTING (MECO), 2020, : 289 - 293
[3] An energy-efficient network-on-chip for a heterogeneous tiled reconfigurable systems-on-chip
Kavaldjiev, N
Smit, GJM
PROCEEDINGS OF THE EUROMICRO SYSTEMS ON DIGITAL SYSTEM DESIGN, 2004, : 492 - 498
[4] Simulating Reconfigurable Multiprocessor Systems-on-Chip with MPSoCSim
Wehner, Philipp
Rettkowski, Jens
Kalb, Tobias
Goehringer, Diana
ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2016, 16 (01)
[5] Providing Accountability in Heterogeneous Systems-on-Chip
Kalayappan, Rajshekar
Sarangi, Smruti R.
ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2018, 17 (05)
[6] Module Relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow
Gantel, L.
Benkhelifa, M. E. A.
Lemonnier, F.
Verdier, F.
2012 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG), 2012,
[7] Stereo vision architecture for heterogeneous systems-on-chip
Stefania Perri
Fabio Frustaci
Fanny Spagnolo
Pasquale Corsonello
Journal of Real-Time Image Processing, 2020, 17 : 393 - 415
[8] A Formal Approach to Accountability in Heterogeneous Systems-on-Chip
Kalayappan, Rajshekar
Sarangi, Smruti R.
IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING, 2021, 18 (06) : 2926 - 2940
[9] Designing reconfigurable multiple scan chains for systems-on-chip
Quasem, MS
Gupta, S
22ND IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2004, : 365 - 371
[10] Stereo vision architecture for heterogeneous systems-on-chip
Perri, Stefania
Frustaci, Fabio
Spagnolo, Fanny
Corsonello, Pasquale
JOURNAL OF REAL-TIME IMAGE PROCESSING, 2020, 17 (02) : 393 - 415

← 1 2 3 4 5 →