An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor

被引：0

作者：

Rahman, Fahim Ur ^{[1
]}

Kim, Sung ^{[1
]}

John, Naveen ^{[1
]}

Kumar, Roshan ^{[1
]}

Li, Xi ^{[1
]}

Pamula, Rajesh ^{[1
]}

Bowman, Keith A. ^{[2
]}

Sathe, Visvesh S. ^{[1
]}

机构：

[1] Univ Washington, Seattle, WA 98195 USA

[2] Qualcomm Technol Inc, Raleigh, NC USA

来源：

2018 IEEE SYMPOSIUM ON VLSI CIRCUITS | 2018年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An all-digital switched-capacitor (SC) based clock frequency (F-clk) and supply voltage (V-dd) regulator unifies F-clk and V-dd generation into a single control loop to reduce the V-dd margin for variations in a sub-threshold ARM Cortex M0 processor. This fully-integrated unified clock and power (Uni-CaP) architecture allows continuous V-dd scalability without a low-dropout (LDO) regulator. Measurements from a 65nm test chip demonstrate a 16% V(dd)( )reduction (94% V-dd margin recovery) and a 3.2x increase in F(clk)( )operating range.

引用

页码：65 / 66

页数：2