Integration of millisecond flash anneal on CMOS devices for DRAM manufacturing

We successfully demonstrate the millisecond flash anneal (MFLA) on a matured DRAM product. The GIDL improvements for array NMOS, periphery N and P MOS are 14.5%,15%, and 39% respectively. The mechanisms of GIDL impact at different process stages have been reviewed. With MFLA replacement, N and PMOS on-current (Ion) gains 4.3% and 11.8% respectively. Superior off current (Ioff) reduction for periphery N and PMOS reach 150% and 500% respectively. Vt roll-off, Vt-lon, Ion-loff correlation, overlap capacitance, and drain induced barrier lowering (DIBL) have been reviewed. TEM data show poly grain enlargement and clustering defects staying at different junction depths. This study shows that MFLA has the benefit for lower thermal budget, high dopant activation, and shallow junction for sub-50nm DRAM.