Simulated fault injection in quantum circuits with the bubble bit technique

被引:4
|
作者
Udrescu, M [1 ]
Prodan, L [1 ]
Vládutiu, M [1 ]
机构
[1] Univ Politehn Timisoara, Adv Comp Syst & Architectures Lab, Timisoara, Romania
来源
ADAPTIVE AND NATURAL COMPUTING ALGORITHMS | 2005年
关键词
D O I
10.1007/3-211-27389-1_66
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
The simulation of quantum circuits is usually exponential. The Hardware Description Languages methodology is able to isolate the entanglement as source of simulation complexity. However, it was shown that this methodology is not efficient unless the bubble bit technique is employed [1]. In this paper, we present an extension of the HDL-bubble bit simulation methodology, which provides means for simulated fault injection - at the unitary level - in quantum circuits. T e purpose is, just like in classical computer hardware design, to be able to verify the effectiveness of the considered quantum circuit fault tolerance methodologies.
引用
收藏
页码:276 / 279
页数:4
相关论文
共 50 条
  • [21] Scalable Fault Coverage Estimation of Sequential Circuits without Fault Injection
    Javvaji, Pavan Kumar
    Tragoudas, Spyros
    Kondapuram, Ganesh
    2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
  • [22] SIMULATED FAULT INJECTION - A METHODOLOGY TO EVALUATE FAULT TOLERANT MICROPROCESSOR ARCHITECTURES
    CHOI, GS
    IYER, RK
    CARRENO, VA
    IEEE TRANSACTIONS ON RELIABILITY, 1990, 39 (04) : 486 - 491
  • [23] The Research Of Memory Fault Simulation And Fault Injection Method For BIT Software Test
    Xu, Jun
    Xu, Ping
    PROCEEDINGS OF THE 2012 SECOND INTERNATIONAL CONFERENCE ON INSTRUMENTATION & MEASUREMENT, COMPUTER, COMMUNICATION AND CONTROL (IMCCC 2012), 2012, : 718 - 722
  • [24] Electromagnetic fault injection: towards a fault model on a 32-bit microcontroller
    Moro, Nicolas
    Dehbaoui, Amine
    Heydemann, Karine
    Robisson, Bruno
    Encrenaz, Emmanuelle
    2013 10TH WORKSHOP ON FAULT DIAGNOSIS AND TOLERANCE IN CRYPTOGRAPHY (FDTC 2013), 2013, : 77 - 88
  • [25] DEDUCTIVE FAULT SIMULATION TECHNIQUE FOR ASYNCHRONOUS CIRCUITS
    Dobai, Roland
    Gramatova, Elena
    COMPUTING AND INFORMATICS, 2010, 29 (06) : 1025 - 1043
  • [26] Test generation and fault localization for quantum circuits
    Perkowski, M
    Biamonte, J
    Lukac, M
    35TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 2005, : 62 - 68
  • [27] Detailed Fault Model for Physical Quantum Circuits
    Deb, Arighna
    Das, Debesh K.
    2019 IEEE 28TH ASIAN TEST SYMPOSIUM (ATS), 2019, : 153 - 158
  • [28] Signal Injection as a Fault Detection Technique
    Cusido, Jordi
    Romeral, Luis
    Antonio Ortega, Juan
    Garcia, Antoni
    Riba, Jordi
    SENSORS, 2011, 11 (03) : 3356 - 3380
  • [29] Cost Optimization Technique for Quantum Circuits
    Anirban Basak
    Arindam Sadhu
    Kunal Das
    Kapil K. Sharma
    International Journal of Theoretical Physics, 2019, 58 : 3158 - 3179
  • [30] Cost Optimization Technique for Quantum Circuits
    Basak, Anirban
    Sadhu, Arindam
    Das, Kunal
    Sharma, Kapil K.
    INTERNATIONAL JOURNAL OF THEORETICAL PHYSICS, 2019, 58 (09) : 3158 - 3179