共 50 条
- [21] The challenges in achieving sub-100nm MOSFETs SECOND ANNUAL IEEE INTERNATIONAL CONFERENCE ON INNOVATIVE SYSTEMS IN SILICON, 1997 PROCEEDINGS, 1997, : 52 - 60
- [22] Variability in sub-100nm SRAM designs ICCAD-2004: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, IEEE/ACM DIGEST OF TECHNICAL PAPERS, 2004, : 347 - 352
- [23] Advances in CPL, collimated plasma source & full field exposure for sub-100nm lithography EMERGING LITHOGRAPHIC TECHNOLOGIES VII, PTS 1 AND 2, 2003, 5037 : 1112 - 1122
- [24] NiSi salicide for sub-100nm CMOS SEMICONDUCTOR SILICON 2002, VOLS 1 AND 2, 2002, 2002 (02): : 354 - 361
- [25] How to print 100 nm contact hole with low NA 193 nm lithography ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XXI, PTS 1 AND 2, 2004, 5376 : 1091 - 1099
- [26] New DFM approach abstracts AItPSM lithography requirements for sub-100nm IC design domains 4TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2003, : 131 - 137
- [27] Patterning sub-100nm features for submicron devices NANOENGINEERED NANOFIBROUS MATERIALS, 2004, 169 : 529 - 534
- [28] Approach for physical design in sub-100nm era 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 5934 - 5937