Chip-package co-design of power distribution network for system-in-package applications

被引:2
|
作者
Kim, GW [1 ]
Kam, DG [1 ]
Chung, DH [1 ]
Kim, JH [1 ]
机构
[1] Korea Adv Inst Sci & Technol, Dept EECS, Terahertz Interconnect & Package Lab, Taejon 305701, South Korea
关键词
D O I
10.1109/EPTC.2004.1396659
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
A new figure of merit for chip-package co-design of a power distribution network (PDN) is needed, not merely a voltage difference between power and ground at each hierarchy. In order to measure power supply noise as it is actually seen by the circuits in various locations on a chip, we need to chase the power/ground voltage with reference to a system ground. A PDN has two current paths; a series path and a shunt path. While the shunt path determines the voltage difference, the series path controls the power/ground voltage itself. Therefore, a balnaced approach is strongly required rather than an excessive attention to the shunt path.
引用
收藏
页码:499 / 501
页数:3
相关论文
共 50 条
  • [41] Design & test of System-in-Package
    Cauvet, P.
    Bernard, S.
    Renovell, M.
    INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS, 2007, 37 (04): : 228 - 234
  • [42] Early Stage Chip/Package/Board Co-design Techniques for System-on-Chip
    Tanaka, Mikiko Sode
    Toyama, Masahiro
    Mori, Ryo
    Nakashima, Hidenari
    Haida, Masahiro
    Ooshima, Izumi
    2011 IEEE 20TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS), 2011, : 21 - 24
  • [43] Chip-package-board co-design for Complex System-on-Chip (SoC)
    Patil, Mahendrasing
    Brahme, Amit
    Shust, Michael
    Coates, Keven
    Thatte, Shubhada
    Soman, Sreekanth
    Kumar, Kamal
    2010 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGE & SYSTEMS SYMPOSIUM, 2010,
  • [44] Chip-Package Thermal Co-Simulation Technique for Thermally Aware Chip Design
    Karimanal, Kamal
    2010 12TH IEEE INTERSOCIETY CONFERENCE ON THERMAL AND THERMOMECHANICAL PHENOMENA IN ELECTRONIC SYSTEMS, 2010,
  • [45] Chip-Package Interaction Challenges for Large Die Applications
    Wu, Zhuo-Jie
    Carey, Charles
    Donavan, Samantha
    Hunt, Doug
    Justison, Patrick
    Anemikos, Theo
    Cincotta, John
    Gagnon, Hugues
    Chacon, Oswaldo
    Martel, Robert
    Wassick, Thomas
    2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018), 2018, : 656 - 662
  • [46] Chip-Package Co-Design of 10 GHz Bandwidth Low Noise Active Front-end Interface
    Fourquin, Olivier
    Battista, Marc
    Cubillo, Joseph Romen
    Gaubert, Jean
    Bourdel, Sylvain
    2009 IEEE 59TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, VOLS 1-4, 2009, : 1612 - 1617
  • [47] Chip-Package Co-Simulation with Multiscale Structures
    Ha, Myunghyun
    Srinivasan, Krishna
    Swaminathan, Madhavan
    2008 IEEE-EPEP ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 2008, : 317 - 320
  • [48] Adaptive chip-package thermal analysis for synthesis and design
    Yang, Yonghong
    Gu, Zhenyu
    Zhu, Changyun
    Shang, Li
    Dick, Robert P.
    2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS, 2006, : 842 - +
  • [49] EMI reduction by chip-package-board co-design
    Kiyoshige, Sho
    Ichimura, Wataru
    Terasaki, Masahiro
    Kobayashi, Ryota
    Sudo, Toshio
    2014 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC EUROPE), 2014, : 946 - 951
  • [50] Chip Package Co-design and Physical Verification for Heterogeneous Integration
    Sankaranarayanan, Rajsaktish
    Srinivasan, Archanna
    Zaliznyak, Arch
    Mittai, Sreelekha
    PROCEEDINGS OF THE 2021 TWENTY SECOND INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2021), 2021, : 275 - 279