A power estimation model for high-speed CMOS A/D converters

被引：11

作者：

Lauwers, E ^{[1
]}

Gielen, G ^{[1
]}

机构：

[1] Katholieke Univ Leuven, Dept Elect Engn, ESAT, MICAS, B-3001 Heverlee, Belgium

来源：

DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/DATE.1999.761155

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Power estimation is important for system-level exploration and trade-off analysis of VLSI systems. A power estimator for high-speed analog to digital converters that exploits information from reported designs is presented. The estimator is an analytical expression which is independent of the actual topology used and can easily be updated with new published designs. Experimental results show a good predictor accuracy of better than a factor 2.2 for most designs.

引用

页码：401 / 405

页数：5

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