In situ fabrication of metal gate/high-κ dielectric gate stacks using a potential lower cost front-end process for the sub-90 nm CMOS technology node

In this article we discuss the advantages of in situ fabrication of metal gate/high-kappa gate stacks using single wafer processing. The aim was to develop an in situ process for the sub-90 nm CMOS regime, which allows for a reduction in the number of processing steps and consequently the number of processing tools, while also providing for improved device performance, yield and reliability. In this work, we demonstrate improved electrical characteristics of ultrathin high dielectric constant films processed by rapid thermal processing (RTP) assisted metal-oxide chemical vapor deposition (MOCVD), where the silicon wafer underwent an in situ precleaning treatment followed by an in situ oxide deposition, in situ oxide anneal, and an in situ metallization step. Gate leakage currents on the order of 10-(11) A /CM2 at a gate voltage of I V and an EOT of 1.5 nm were measured across the A1(2)0(3) gate oxide of the gate stacks. These results present an improvement of two orders of magnitude over gate leakage currents measured across A1(2)0(3) gate oxides with comparable EOT values reported in literature. (c) 2005.