Long unsigned number systolic serial multipliers and squarers

被引：11

作者：

Pekmestzi, KZ ^{[1
]}

Kalivas, P ^{[1
]}

Moshopoulos, N ^{[1
]}

机构：

[1] Natl Tech Univ Athens, Dept Elect & Comp Engn, Athens, Greece

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 2001年 / 48卷 / 03期

关键词：

serial multiplier; serial squarer; systolic circuits;

D O I：

10.1109/82.924075

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A systolic serial multiplier and a squarer for unsigned numbers-which operate without zero words inserted between successive data words, output the full product, and have only one clock cycle latency-are presented. The multiplier is based on a modified serial/parallel scheme that operates with 100% efficiency. The systolic form is obtained by merging two adjacent multiplier cells. The same technique is used for the design of a serial squarer. The systolisity and the continuous operation are achieved without an increase in hardware complexity. The proposed schemes are well suited for long number multiplication and squaring.

引用

页码：316 / 321

页数：6

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