Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core

被引:5
|
作者
Rodrigues, Rance [1 ]
Koren, Israel [1 ]
Kundu, Sandip [1 ]
机构
[1] Univ Massachusetts, Dept Elect & Comp Engn, Amherst, MA 01003 USA
关键词
Asymmetric Multicore Processor (AMP); Symmetric Multicore Processor (SMP); resource sharing; performance; performance/Watt;
D O I
10.1109/VLSID.2014.42
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Several studies and real world designs have advocated the sharing of large execution units between pairs of cores in Symmetric Multicore Processors (SMP) for area and power savings. Such sharing was shown to have negligible impact on performance. Recently, a number of Asymmetric Multicore Processor (AMP) designs have become available. The objective of this paper is to investigate whether sharing of resources across AMPs offers similar benefits. Our study shows that while the area and the power savings remain similar, the performance of the smaller core in the AMP can improve significantly making sharing even more attractive for AMPs. Simulation results indicate that for certain workloads, the performance of the small core may improve by as much as 54% by sharing certain large execution resources of the big core, while affecting the performance of the big core by only similar to 4%, resulting in an overall gain in system performance of 20%. The corresponding improvement in aggregate performance/Watt is 12% while the area savings is about 7%.
引用
收藏
页码:204 / 209
页数:6
相关论文
共 50 条
  • [21] MnZn power ferrite with high Bs and low core loss
    Liu, Dong
    Chen, Xiaping
    Ying, Yao
    Zhang, Ling
    Li, Wangchang
    Jiang, Liqiang
    Che, Shenglei
    CERAMICS INTERNATIONAL, 2016, 42 (07) : 9152 - 9156
  • [22] Hardware Implementation Low Power High Speed FFT Core
    Kannan, Muniandi
    Srivatsa, Srinivasa
    INTERNATIONAL ARAB JOURNAL OF INFORMATION TECHNOLOGY, 2009, 6 (01) : 1 - 6
  • [23] A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications
    Bora, Satyajit
    Paily, Roy
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68 (06) : 2132 - 2136
  • [24] Unleashing the High-performance and Low-power of Multi-core DSPs for General-purpose HPC
    Igual, Francisco D.
    Ali, Murtaza
    Wentz, Timothy
    van de Geijn, Robert A.
    2012 INTERNATIONAL CONFERENCE FOR HIGH PERFORMANCE COMPUTING, NETWORKING, STORAGE AND ANALYSIS (SC), 2012,
  • [25] Selective-sets resizable cache memory design for high-performance and low-power CPU core
    Kurafuji, T
    Nakase, Y
    Takata, H
    Imamura, Y
    Akiyama, R
    Yamanaka, T
    Iwabu, A
    Yasuda, S
    Miwa, T
    Nunomura, Y
    Itoh, N
    Kagemoto, T
    Yoshioka, N
    Shibagaki, T
    Kondo, H
    Koyama, M
    Arakawa, T
    Iwade, S
    IEICE TRANSACTIONS ON ELECTRONICS, 2004, E87C (04): : 535 - 542
  • [26] A low power FIR filtering core
    Erdogan, AT
    Hasan, M
    Arslan, T
    14TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2001, : 271 - 275
  • [27] Design method of high performance and low power functional units considering delay variations
    Watanabe, Kouichi
    Imai, Masashi
    Kondo, Masaaki
    Nakamura, Hiroshi
    Nanya, Takashi
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2006, E89A (12): : 3519 - 3528
  • [28] In-core power prediction and effects of average core temperature on miniature neutron source reactor's core performance
    Anas, M.S.
    Ahmed, Y.A.
    Rabiu, Nasiru
    Agbo, S.A.
    Balarabe, Bala
    International Journal of Nuclear Energy Science and Technology, 2015, 9 (04) : 279 - 292
  • [29] High Power Density PMSM With Lightweight Structure and High-Performance Soft Magnetic Alloy Core
    Fang, Shuhua
    Liu, Huan
    Wang, Haitao
    Yang, Hui
    Lin, Heyun
    IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2019, 29 (02)
  • [30] High performance low power low voltage adder
    Wu, A
    Ng, CK
    ELECTRONICS LETTERS, 1997, 33 (08) : 681 - 682