Technology scaling effects on the ESD design parameters in sub-100nm CMOS transistors

被引：0
|
作者：
Boselli, G [1 ]
Rodriguez, J [1 ]
Duvvury, C [1 ]
Reddy, V [1 ]
Chidambaram, PR [1 ]
Hornung, B [1 ]
机构：
[1] Texas Instruments Inc, Silicon Technol Dev, Dallas, TX 75243 USA
来源：
2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST | 2003年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A new phenomenon, reported in this paper for the first time, produces a dramatic reduction of the nMOS and pMOS triggering voltage (VT,) under ESD conditions for an ultra-scaled 90nm CMOS technology used in high performance applications. This VT, reduction is caused by the merging of pocket implants in short gate length transistors. This has a serious impact on the ESD sensitivity of output drivers,. placing restrictions on the design of effective protection devices and burn-in voltage during product screening.
引用
收藏
页码：507 / 510
页数：4
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