A single chip, ultra high-speed FFT architecture

被引：4

作者：

Zhong, K ^{[1
]}

Zhu, GX ^{[1
]}

He, H ^{[1
]}

机构：

[1] Huazhong Univ Sci & Technol, Dept Elect & Informat Engn, Wuhan 430074, Peoples R China

来源：

2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/ICASIC.2003.1277320

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a single chip ultra high-speed FFT architecture for real-time signal processing based on radix-8 algorithm. In order to meet Such a data sample rate as several hundred MHZ. high-speed differential I/O interfaces and dedicated block-pipelined architecture are adopted. This idea is supported by a design example. operated at a frequency: of 100MHZ, a FFT processor based on this architecture can calculate a 512-point complex FFT in 0,625us.

引用

页码：752 / 756

页数：5

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