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- [21] Mass-productive ultra-low temperature ALD SiO2 process promising for sub-90nm memory and logic devices INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, 2002, : 229 - 232
- [22] Advance of resist profile control in multi-layer resist process for sub-150 nm lithography ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XV, PTS 1 AND 2, 1998, 3333 : 347 - 356
- [23] Development of sub-half micrometric structures with high aspect ratio using a multi-layer lithography e-beam process and plasma dry etching MOLECULAR CRYSTALS AND LIQUID CRYSTALS, 2002, 374 : 167 - 172
- [24] Experimental Demonstration of Performance Enhancement of MFMIS and MFIS for 5-nm x 12.5-nm Poly-Si Nanowire Gate-All-Around Negative Capacitance FETs Featuring Seed-Layer and PMA-Free Process 2019 SILICON NANOELECTRONICS WORKSHOP (SNW), 2019, : 97 - 98