CMOS built-in test architecture for high-speed jitter measurement

被引：0

作者：

Lin, HC ^{[1
]}

Taylor, K ^{[1
]}

Chong, A ^{[1
]}

Chan, E ^{[1
]}

Soma, M ^{[1
]}

Haggag, H ^{[1
]}

Huard, J ^{[1
]}

Braatz, J ^{[1
]}

机构：

[1] Univ Washington, Dept Elect Engn, Seattle, WA 98195 USA

来源：

INTERNATIONAL TEST CONFERENCE 2003, PROCEEDINGS | 2003年

关键词：

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

A BIST method measures accumulated jitter over N periods and requires no external references. Simulation using a 0.25um process shows a 625MHz-1GHz input range with resolution of 76ps RMS jitter occupying 0.0575mm(2) area.

引用

页码：67 / 76

页数：10

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