共 50 条
- [34] A low-power VLSI implementation for variable length decoder in MPEG-1 layer III EMBEDDED PROCESSORS FOR MULTIMEDIA AND COMMUNICATIONS, 2004, 5309 : 30 - 39
- [35] Evaluating a low-power dual-core architecture ADVANCED PARALLEL PROCESSING TECHNOLOGIES, PROCEEDINGS, 2007, 4847 : 80 - 89
- [36] Realization and optimization of H.264 decoder for dual-core soc SIGMAP 2007: PROCEEDINGS OF THE SECOND INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND MULTIMEDIA APPLICATIONS, 2007, : 309 - +
- [37] On the implementation of interior point methods for dual-core platforms OPTIMIZATION METHODS & SOFTWARE, 2010, 25 (03): : 449 - 456
- [38] Analyses of the coupled architecture of dual-core embedded processor Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology, 2003, 25 (SUPPL.):
- [39] Design and Implementation of a Videotext Extractor on Dual-core Platform 2008 IEEE ASIA-PACIFIC SERVICES COMPUTING CONFERENCE, VOLS 1-3, PROCEEDINGS, 2008, : 896 - 900