Deadline constrained cyclic scheduling on pipelined dedicated processors considering multiprocessor tasks and changeover times

This paper presents a scheduling technique used to optimize computation speed of loops running on architectures that may include pipelined dedicated processors. The problem under consideration is to find an optimal periodic schedule satisfying the timing constraints. Motivated by FPGA (Field-Programmable Gate Array) architecture we formulate a problem of cyclic scheduling on one dedicated processor where tasks are constrained by the precedence delays. Further we generalize this result to the set of dedicated processors. We also show how the set of constraints in both problems can be extended by start time related deadlines, multiprocessor tasks, changeover times and minimization of data transfers. We prove that this problem is NP-hard by reduction from Bratley's scheduling problem 1 vertical bar r(j), (d) over tilde (j)vertical bar C-max and we suggest a solution based on ILP (Integer Linear Programming) that allows one to minimize the completion time. Besides this, we suggest elimination of redundant constraints and binary variables in a integer linear programming model which leads to a speedup of the scheduling algorithm. Finally, experimental results are shown on an application of recursive least square filter and benchmarks. (c) 2007 Elsevier Ltd. All rights reserved.