Reduction of Thermal Stress in Copper TSV due to Annealing by Low TEC Copper

被引：1

作者：

Dinh, V. Q. ^{[1
,2
]}

Kondo, K. ^{[1
]}

Hirato, T. ^{[2
]}

机构：

[1] Fine Feature Electrodeposit Res Lab, Osaka 5941157, Japan

[2] Kyoto Univ, Dept Energy Sci & Technol, Kyoto 6068501, Japan

来源：

MATERIALS, FORMULATION, AND PROCESSES FOR SEMICONDUCTOR, 2.5 AND 3D CHIP PACKAGING, AND HIGH DENSITY INTERCONNECTION PCB | 2018年 / 86卷 / 08期

关键词：

D O I：

10.1149/08608.0017ecst

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Copper through-silicon via (TSV) is the key technology used in 3D packaging. During the fabrication process, copper TSV is exposed to a high temperature between 400 degrees C and 600 degrees C. For conventional copper TSV, we observed the cracks at the bottom of TSV after annealing at 500 degrees C and a very high copper extrusion height, which destroys the overlying layers above the TSV. We also succeeded to prevent cracks at the bottom of the TSV and reduce the copper extrusion height by using the low thermal expansion coefficient (TEC) copper.

引用

页码：17 / 21

页数：5

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