High-Throughput LDPC-CC Decoders Based on Storage, Arithmetic, and Control Improvements

This brief presents high-throughput low-density parity-check convolutional code (LDPC-CC) decoders in full compliance with the IEEE 1901 standard. The decoding architecture is improved from storage, arithmetic, and control aspects. First, to address the throughput bottleneck caused by memory bandwidth, we propose two methods, register-based and categorized memory-based (CMem-based) storage schemes. Then, the arithmetic improvement is extensively exploited for better area. Besides, the control unit is well-designed to reduce the hardware complexity. Equipped with these techniques, efficient LDPC-CC decoders for IEEE 1901 standard are developed and implemented with 55nm technology. Implementation results demonstrate that the proposed decoders can achieve more than twice the throughput of existing decoders. Furthermore, the proposed CMem-based decoder improves the area efficiency by 84.5%.