An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems

This paper presents a multimode FFT processor for wireless personal area network (WPAN), wireless local area network (WLAN), and wireless metropolitan area network (WMAN) applications. Using the proposed flexible-radix-configuration multipath-delay-feedback (FRCMDF) architecture, variable-length/multiple-stream FFTs capable of achieving a high throughput can be performed in a hardware-efficient manner. Based on the FRCMDF structure, a dual-optimized multiplication scheme is also proposed to further improve the area and energy efficiency. In addition, the proposed configuration scheme can provide an architectural support for power scalability across FFT modes. A test chip for the proposed FFT processor has been designed and fabricated using a TSMC-0.18 mu m CMOS process with a core size of 3.2 mm(2) and a signal-to-quantization-noise ratio (SQNR) of over 40 dB. When the FFT mode is configured to operate as a 2.4 GS/s 512-point FFT at 300 MHz, the measured power consumption is 507 mW. Compared with previous multimode FFT designs, our FFT chip is more area- and energy-efficient as it is able to provide relatively higher throughput per unit area or per unit power consumption. Also, the power scalability across FFT modes is relatively exhibited in the proposed FFT processor.