Modeling of Reconfigurable ΣΔ Modulator for Multi-standard Wireless Receivers in Verilog-A

被引:0
|
作者
Castro, Mateus [1 ]
Souza, Raphael [1 ]
Junior, Agord [1 ]
Lima, Eduardo [2 ]
Manera, Leandro [1 ]
机构
[1] Univ Estadual Campinas, Campinas, SP, Brazil
[2] Eldorado Res Inst, Campinas, SP, Brazil
关键词
D O I
10.1109/SBCCI53441.2021.9529972
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents the modeling and design of a reconfigurable Sigma Delta modulator in Verilog-A language for applications in multi-standard wireless receivers. Main building blocks are implemented separately and its development detailed. Results presented are from simulations in SPECTRE circuit simulator in Cadence Virtuoso Analog Design Environment using Verilog-A models of main sub-circuits. The modulator achieves SNR values of 78.7 dB for GSM (EDGE) operation (200 kHz bandwidth), 79.9 dB for Bluetooth operation (500 kHz bandwidth) and 55.3 dB for UMTS (W-CDMA) operation (2 MHz bandwidth).
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页数:6
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