A dynamic logic circuit embedded flip-flop for asic design

被引：0

作者：

Hirairi, K ^{[1
]}

Kosaka, H ^{[1
]}

Moriki, K ^{[1
]}

Keino, K ^{[1
]}

Onuma, K ^{[1
]}

机构：

[1] Sony Corp, Platform SOC Solut Ctr, Shinagawa Ku, Tokyo 1410032, Japan

来源：

PROCEEDINGS OF THE SECOND IEEE ASIA PACIFIC CONFERENCE ON ASICS | 2000年

关键词：

D O I：

10.1109/APASIC.2000.896898

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report a flip-flop with a dynamic logic circuit for data path designed with standard cell. The flip-flop provides fast logic operation by the dynamic logic circuit and reduces total power dissipation of a data path by suppressing glitches. An absolute difference unit for motion estimation is used in a benchmark test. By using the flip-flop, the unit is 20% to 40% faster and has 20% to 50% less power dissipation than when conventional D-FFs are used.

引用

页码：21 / 24

页数：4

共 50 条

[31] Robust flip-flop circuit against soft errors for combinational and sequential logic circuits
Fujitsu Microelectronics Ltd., 1500 Mizono, Tado, Kuwana, Mie 511-0192, Japan
不详
Jpn. J. Appl. Phys., 1600, 4 PART 2
[32] Clock, Flip-Flop, and Combinatorial Logic Contributions to the SEU Cross Section in 90 nm ASIC Technology
Hansen, David L.
Miller, Eric J.
Kleinosowski, Aj
Kohnen, Kirk
Le, Anthony
Wong, Dick
Amador, Karina
Baze, Mark
DeSalvo, David
Dooley, Maryanne
Gerst, Kenneth
Hughlock, Barrie
Jeppson, Bradford
Jobe, R. D.
Nardi, David
Ojalvo, Isabel
Rasmussen, Brad
Sunderland, David
Truong, John
Yoo, Michael
Zayas, E.
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2009, 56 (06) : 3542 - 3550
[33] A New Design of Static Double Edge-Triggered Flip-Flop Circuit
Yu Chien-Cheng
2008 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1 AND 2, 2008, : 1195 - 1198
[34] An alternative approach of optical flip-flop with tristate logic
Ghosh, P
Das, DN
Mukhopadhyay, S
INDIAN JOURNAL OF PURE & APPLIED PHYSICS, 1998, 36 (04) : 224 - 227
[35] A 65 nm Temporally Hardened Flip-Flop Circuit
Li, Y. -Q.
Wang, H. -B.
Liu, Rui
Chen, Li
Nofal, Issam
Chen, Q. -Y.
He, A. -L.
Guo, Gang
Baeg, Sang H.
Wen, Shi-Jie
Wong, Richard
Wu, Qiong
Chen, Mo
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2016, 63 (06) : 2934 - 2940
[36] A low-power edge-triggered and logic-embedded flip-flop using complementary pass transistor circuit
Park, KT
Mizukusa, T
Won, HS
Kurino, H
Koyanagi, M
IEICE TRANSACTIONS ON ELECTRONICS, 2004, E87C (04) : 640 - 644
[37] Design and implementation of dynamic logic gates and R-S flip-flop using quasiperiodically driven Murali-Lakshmanan-Chua circuit
Venkatesh, P. R.
Venkatesan, A.
Lakshmanan, M.
CHAOS, 2017, 27 (03)
[38] Switched flip-flop based preprocessing circuit for ISFETs
Kollár, M
SENSORS, 2005, 5 (03): : 118 - 125
[39] PREDICTION OF INTEGRATED FLIP-FLOP CIRCUIT RADIATION VULNERABILITY
CHANG, WW
RAYMOND, JP
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1967, NS14 (06) : 223 - &
[40] Self-blocking flip-flop design
Li, X.
Jia, S.
Liang, X.
Wang, Y.
ELECTRONICS LETTERS, 2012, 48 (02) : 82 - U50

← 1 2 3 4 5 →