A dynamic logic circuit embedded flip-flop for asic design

被引：0

作者：

Hirairi, K ^{[1
]}

Kosaka, H ^{[1
]}

Moriki, K ^{[1
]}

Keino, K ^{[1
]}

Onuma, K ^{[1
]}

机构：

[1] Sony Corp, Platform SOC Solut Ctr, Shinagawa Ku, Tokyo 1410032, Japan

来源：

PROCEEDINGS OF THE SECOND IEEE ASIA PACIFIC CONFERENCE ON ASICS | 2000年

关键词：

D O I：

10.1109/APASIC.2000.896898

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report a flip-flop with a dynamic logic circuit for data path designed with standard cell. The flip-flop provides fast logic operation by the dynamic logic circuit and reduces total power dissipation of a data path by suppressing glitches. An absolute difference unit for motion estimation is used in a benchmark test. By using the flip-flop, the unit is 20% to 40% faster and has 20% to 50% less power dissipation than when conventional D-FFs are used.

引用

页码：21 / 24

页数：4

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