共 24 条
- [1] Type-4 2-D Diagonal and Four-Fold Rotational Symmetry Digital Filter Architectures 2018 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2018), 2018, : 115 - 118
- [3] ASIC Implementation of Area-Efficient, High-Throughput 2-D IIR Filter Using Distributed Arithmetic Circuits, Systems, and Signal Processing, 2018, 37 : 2934 - 2957
- [4] Area-efficient 2-D shift-variant convolvers for FPGA-based digital image processing 2005 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS - DESIGN AND IMPLEMENTATION (SIPS), 2005, : 209 - 213
- [6] Architecture for area-efficient 2-D transform in H.264/AVC 2005 IEEE International Conference on Multimedia and Expo (ICME), Vols 1 and 2, 2005, : 1127 - 1130
- [7] High-Throughput, Area-Efficient Architecture of 2-D Block FIR Filter Using Distributed Arithmetic Algorithm Circuits, Systems, and Signal Processing, 2019, 38 : 1099 - 1113