An FPGA-based eigenfilter using fast Hebbian learning

We present a high-gain, multiple learning/decay rate, "cooling off' annealing strategy to a modified Generalized Hebbian Algorithm (GHA) that gives good approximate solution within one training epoch, and with fast convergence to accurate principal components within a few more epochs. A novel bit-shifting normalization procedure is shown to bound the weight vector norm effectively and eliminates the need for performing division. This leads to an FPGA-based computational framework using only fixed point arithmetic instead of more complicated floating point design. Simulation results on Xilinx DSP System Generator tool indicate the practicality of the approach, where real-time eigenfilter can be readily implemented on field programmable gate arrays with limited resources.