Low power digital filters based on constrained least squares solution

In this paper, we investigate a top-down design strategy for reducing the number of operations in digital filters based on a constrained least squares (CLS) solution. The proposed strategy reduces switching activity in the VLSI implementation of such Alters by constraining the Hamming weight (KW) of coefficients, thereby, restricting the number of power consuming operations required to compute the output. The pourer constrained least squares (PCLS) coefficients obtained from the original coefficients can be used in conjunction with appropriately modified multipliers to reduce power consumption. We also show that for filters designed using least squares (LS) method, the solution obtained using the proposed method is an optimal solution to the operations constrained by LS problem. Finally, we extend this approach to adaptive Alters based on LS method.