共 47 条
- [41] A 40Gb/s 39mW 3-tap Adaptive Closed-loop Decision Feedback Equalizer in 65nm CMOS 2015 IEEE 58TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2015,
- [43] A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
- [44] A 10Gb/s 10mm On-Chip Serial Link in 65nm CMOS Featuring a Half-Rate Time-Based Decision Feedback Equalizer 2017 SYMPOSIUM ON VLSI CIRCUITS, 2017, : C56 - C57
- [46] A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor 2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), 2020, : 336 - +
- [47] A 10 Gb/s adaptive analog decision feedback equalizer for multimode fiber dispersion compensation in 0.13 μ\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$${\upmu }$$\end{document}m CMOS Analog Integrated Circuits and Signal Processing, 2015, 83 (2) : 271 - 283