Workload distribution in fault simulation

被引：10

作者：

Amin, MB ^{[1
]}

Vinnakota, B ^{[1
]}

机构：

[1] UNIV MINNESOTA, DEPT ELECT ENGN, MINNEAPOLIS, MN 55455 USA

来源：

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 1997年 / 10卷 / 03期

基金：

美国国家科学基金会;

关键词：

fault simulation; logic simulation; parallel simulation; parallelization; workload distribution;

D O I：

10.1023/A:1008275810655

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Simulation at the gate level is computationally very expensive. Parallel processing is one technique to reduce simulation time. Possessing knowledge of the distribution of computational activity in simulation can aid in parallelizing it efficiently. We present a new characterization of the distribution of the computational workload in fault simulation. An empirical analysis shows that the workload distribution is circuit specific, and is largely independent of the vector set being simulated. An inexpensive method to predict the workload distribution is also discussed.

引用

页码：277 / 282

页数：6

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