A 0.11 μm CMOS technology with copper and very-low-k interconnects for high-performance system-on-a chip cores

This paper describes a 0.11 mu m CMOS technology with high-reliable copper and very-low-k (VLK) (k<2.7) interconnects for high performance and low power applications. Aggressive design rules, 0.11 <mu> m gate transistor, and 2.2 mu m(2) 6T-SRAM cell are realized by using KrF 248nm lithography, optical-proximity-effect correction (OPC), and gate-shrink techniques. Drain current of 0.63mA/ mu m and 0.28mA/ mu m are realized for nMOSFET and pMOSFET with 0.11 mu m gate, respectively. Propagation delay of 2-input NAND with the copper/hybrid VLK interconnects is estimated. The delay is improved by more than 70%, compared to 0.18 mu m CMOS technology with copper/FSG interconnects.