A Heterogeneous 3D-IC Consisting of Two 28nm FPGA Die and 32 Reconfigurable High-Performance Data Converters

被引：0

作者：

Erdmann, Christophe ^{[1
]}

Lowney, Donnacha ^{[1
]}

Lynam, Adrian ^{[1
]}

Keady, Aidan ^{[1
]}

McGrath, John ^{[1
]}

Cullen, Edward ^{[1
]}

Breathnach, Daire ^{[1
]}

Keane, Denis ^{[1
]}

Lynch, Patrick ^{[1
]}

De La Torre, Marites ^{[1
]}

De La Torre, Ronnie ^{[1
]}

Lim, Peng ^{[1
]}

Collins, Anthony ^{[1
]}

Farley, Brendan ^{[1
]}

Madden, Liam ^{[2
]}

机构：

[1] Xilinx, Dublin, Ireland

[2] Xilinx, San Jose, CA USA

来源：

2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC) | 2014年 / 57卷

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：120 / +

页数：3

共 8 条

[1] A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters
Erdmann, Christophe
Lowney, Donnacha
Lynam, Adrian
Keady, Aidan
McGrath, John
Cullen, Edward
Breathnach, Daire
Keane, Denis
Lynch, Patrick
De La Torre, Marites
De La Torre, Ronnie
Lim, Peng
Collins, Anthony
Farley, Brendan
Madden, Liam
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2015, 50 (01) : 258 - 269
[2] Assembly and Reliability Challenges in 3D Integration of 28nm FPGA Die on a Large High Density 65nm Passive Interposer
Chaware, Raghunandan
Nagarajan, Kumar
Ramalingam, Suresh
2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2012, : 279 - 283
[3] Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking
Chen, D. Y.
Chiou, W. C.
Chen, M. F.
Wang, T. D.
Ching, K. M.
Tu, H. J.
Wu, W. J.
Yu, C. L.
Yang, K. F.
Chang, H. B.
Tseng, M. H.
Hsiao, C. W.
Lu, Y. J.
Hu, H. P.
Lin, Y. C.
Hsu, C. S.
Shue, Winston S.
Yu, C. H.
2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, 2009, : 327 - 330
[4] High-Performance, Cost-Effective Heterogeneous 3D FPGA Architectures
Le, Roto
Reda, Sherief
Bahar, R. Iris
GLSVLSI 2009: PROCEEDINGS OF THE 2009 GREAT LAKES SYMPOSIUM ON VLSI, 2009, : 251 - 256
[5] 28nm High-K Metal Gate Heterogeneous Quad-core CPUs for High-performance and Energy-efficient Mobile Application Processor
Shin, Youngmin
Lee, Hoi-Jin
Shin, Ken
Kenkae, Prashant
Kashyap, Rajesh
Seo, DongJoo
Millar, Brian
Kwon, Yohan
Iyengar, Ravi
Kim, Min-su
Chowdhury, Ahsan
Bae, Sung-il
Hong, Inpyo
Jeong, Wookyeong
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Son, Jae Cheol
Park, Sung Ho
2013 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2013, : 198 - 201
[6] 28nm High-κ Metal-Gate Heterogeneous Quad-Core CPUs for High-Performance and Energy-Efficient Mobile Application Processor
Shin, Youngmin
Shin, Ken
Kenkare, Prashant
Kashyap, Rajesh
Lee, Hoi-Jin
Seo, Dongjoo
Millar, Brian
Kwon, Yohan
Iyengar, Ravi
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[7] A larger stacked layer number scalable TSV-based 3D-SRAM for high-performance universal-memory-capacity 3D-IC platforms
National Tsing Hua University, Taiwan
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IEEE Symp VLSI Circuits Dig Tech Pap, 2011, (74-75):
[8] A 14nm Finfet Transistor-Level 3D Partitioning Design to Enable High-Performance and Low-Cost Monolithic 3D IC
Shi, Jiajun
Nayak, Deepak
Banna, Srinivasa
Fox, Robert
Samavedam, Srikanth
Samal, Sandeep
Lim, Sung Kyu
2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2016,

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