Scalable Hardware Content Router: Architecture, Modeling and Performance

被引:0
|
作者
Liu, Bin [1 ]
Dai, Huichen [1 ]
Xu, Wenquan [1 ]
Yun, Tong [1 ]
Miao, Ji [1 ]
机构
[1] Tsinghua Univ, Dept Comp Sci & Technol, Beijing, Peoples R China
关键词
D O I
10.1109/IWQOS52092.2021.9521334
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Current Internet is evolving with the gradual shift from the traditional host-to-host communication model to the new host-to-content paradigm, which will eventually lead to a network of caches. The novel Named Data Networking (NDN) has been proposed as a future Internet architecture to embrace this paradigmatic shift, where caching becomes an ubiquitous functionality available at each router. A router with the functionality of content caching, running on NDN mechanisms, is termed as an NDN-based content router. Previous researchers focused on software content routers (SCR), which leverage a commercial off-the-shelf computer to execute content caching/accessing and named-based packet forwarding. SCR can only achieve limited throughput, which is far below the speed requirements of modern routers. Facing this situation, in this paper, we propose a hardware-based content router (HCR), aiming at purchasing wire-speed processing. We design a physically concise architecture for decoupling the packet buffers in line cards from the content caches attached to storage cards, enabling separate management and optimization while facilitating a modular structure for smooth capacity upgrade in response to increasing storage utilization. For lowering the operating complexity and reducing the storage management cost, we choose to employ distributed caches working in a cooperated manner by using consistent hashing. We model several candidate storage organizing schemes and carry out theoretical analyses for comparison. Analytical and synthetic workload-driven results show that the consistent hashing scheme achieves high cache performance and low cost simultaneously.
引用
收藏
页数:7
相关论文
共 50 条
  • [31] Router Architecture for High-Performance NoCs
    Carara, Everton
    Calazans, Ney
    Moraes, Fernando
    SBCCI2007: 20TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, 2007, : 111 - 116
  • [32] A high performance router architecture for multimedia applications
    Orduna, JM
    Duato, J
    FIFTH INTERNATIONAL CONFERENCE ON MASSIVELY PARALLEL PROCESSING, PROCEEDINGS, 1998, : 142 - 149
  • [33] A Scalable Approach to Modeling on Accelerated Neuromorphic Hardware
    Mueller, Eric
    Arnold, Elias
    Breitwieser, Oliver
    Czierlinski, Milena
    Emmel, Arne
    Kaiser, Jakob
    Mauch, Christian
    Schmitt, Sebastian
    Spilger, Philipp
    Stock, Raphael
    Stradmann, Yannik
    Weis, Johannes
    Baumbach, Andreas
    Billaudelle, Sebastian
    Cramer, Benjamin
    Ebert, Falk
    Goeltz, Julian
    Ilmberger, Joscha
    Karasenko, Vitali
    Kleider, Mitja
    Leibfried, Aron
    Pehle, Christian
    Schemmel, Johannes
    FRONTIERS IN NEUROSCIENCE, 2022, 16
  • [34] Performance Modeling and Analysis of an Autonomic Router
    Gribaudo, Marco
    Campanile, Lelio
    Iacono, Mauro
    Mastroianni, Michele
    PROCEEDINGS OF THE 33RD INTERNATIONAL ECMS CONFERENCE ON MODELLING AND SIMULATION (ECMS 2019), 2019, 33 (01): : 441 - 447
  • [35] Design and performance analysis of a modular and scalable optical access router
    Wang, TS
    LEOS 2001: 14TH ANNUAL MEETING OF THE IEEE LASERS & ELECTRO-OPTICS SOCIETY, VOLS 1 AND 2, PROCEEDINGS, 2001, : 163 - 164
  • [36] Hardware-and-software-based security architecture for broadband router (short paper)
    Gu Xiaozhuo
    Li Yufeng
    Yang Jianzu
    Lan Julong
    Information and Communications Security, Proceedings, 2006, 4307 : 546 - 555
  • [37] Scalable router memory architecture based on interleaved DRAM: Analysis and numerical studies
    Wang, Feng
    Hamdi, Mounir
    2007 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, VOLS 1-14, 2007, : 6380 - 6385
  • [38] Scalable Multi-QoS IP plus ATM switch router architecture
    Shiomoto, K
    Uga, M
    Omotani, M
    Shimizu, S
    Chimaru, T
    IEEE COMMUNICATIONS MAGAZINE, 2000, 38 (12) : 86 - 92
  • [39] Modeling, hardware architecture, and performance analyses of an AEAD-based lightweight cipher
    Jhawar, Kartik
    Gandhi, Jugal
    Shekhawat, Diksha
    Upadhyay, Aniket
    Harkishanka, Avadh
    Chaturvedi, Nitin
    Santosh, M.
    Pandey, Jai Gopal
    JOURNAL OF REAL-TIME IMAGE PROCESSING, 2024, 21 (02)
  • [40] Modeling, hardware architecture, and performance analyses of an AEAD-based lightweight cipher
    Kartik Jhawar
    Jugal Gandhi
    Diksha Shekhawat
    Aniket Upadhyay
    Avadh Harkishanka
    Nitin Chaturvedi
    M. Santosh
    Jai Gopal Pandey
    Journal of Real-Time Image Processing, 2024, 21