Memory efficient implementation of AES S-BOXES on FPGA

被引：15

作者：

Aziz, Arshad ^{[1
]}

Ikram, Nassar ^{[1
]}

机构：

[1] NUST, Dept Elect Engn, Karachi 75350, Pakistan

来源：

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 2007年 / 16卷 / 04期

关键词：

cryptography; AES; S-box; FPGA; verilog;

D O I：

10.1142/S0218126607003873

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Optimized implementation of computationally intensive cryptographic transformation is an area of active research, mainly focused on Advanced Encryption Standard (AES). Byte substitution implemented using substitution boxes (S-boxes), is the main transformation in AES which strains the enabling embedded platform, e. g., Field Programmable Gate Arrays. We represent a novel clocking technique enabling optimized implementation of Byte Substitution that enhances processing speed and reduces the area required for S-boxes on Xilinx FPGA Block RAM (BRAM).

引用

页码：603 / 611

页数：9

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