Variation-Aware Task and Communication Scheduling in MPSoCs for Power-Yield Maximization

Parameter variations reveal themselves as different frequency and leakage powers per instances of the same MPSoC By the increasing variation with technology scaling worst case based scheduling algorithms result in either increasingly less optimal schedules or otherwise more lost yield To address this problem this paper introduces a variation aware task and communication scheduling algorithm for multiprocessor system on chip (MPSoC) We consider both delay and leakage power van awns during the process of finding the best schedule so that leakier processors are less utilized and can be more frequently put in sleep mode to reduce power Our algorithm takes advantage of event tables to accelerate the statistical timing and power analysis We use genetic algorithm to find the best schedule that maximizes power yield under a performance yield constraint Experimental results on real world benchmarks show that our proposed algorithm achieves 16 6% power yield improvement on average over deterministic worst case based scheduling