A 4 mW 3-5 GHz current reuse gm-boosted short channel common-gate CMOS UWB LNA

A novel architecture is presented to optimize the noise performance and the power consumption of the transconductance 'g(m)' boosted common-gate (CG) ultrawideband (UWB) low-noise amplifier (LNA), operating in the 3-5 GHz range, by employing current reuse technique. This proposed CG LNA utilizes a common source (CS) amplifier as the g(m)-boosting stage and the bias current is shared between the g(m)-boosting stage and the CG amplifying stage. The LNA circuit also utilizes the short channel conductance g(ds) in conjunction with an LC T-network to further reduce the noise figure (NF). The proposed LNA architecture has been fabricated using the 130 nm IBM CMOS process. The LNA achieved input return loss (S-11) of -8 to -10 dB, and, output return loss (S-22) of -12 to -14 dB, respectively. The LNA exhibits almost flat forward voltage gain (S-21) of 13 dB, and reverse isolation (S-12) of -62 to -49 dB, with a NF ranging between 3.8 and 4.6 dB. The measurements indicate an input-referred third order intercept point (IIP3) of -6.1 dBm and an input-referred 1-dB compression point (ICP1dB) of -15.4 dBm. The complete chip draws 4 mW of DC power from a 1.2 V supply.