Raised source/drain (RSD) for 50nm MOSFETs - Effect of epitaxy layer thickness on short channel effects.

被引:4
|
作者
Waite, AM [1 ]
Lloyd, NS [1 ]
Ashburn, P [1 ]
Evans, AGR [1 ]
Ernst, T [1 ]
Achard, H [1 ]
Deleonibus, S [1 ]
Wang, Y [1 ]
Hemment, P [1 ]
机构
[1] Univ Southampton, Dept Elect & Comp Sci, Southampton SO17 1BJ, Hants, England
来源
ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2003年
关键词
D O I
10.1109/ESSDERC.2003.1256854
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We present raised source drain MOSFET devices with channel lengths down to 50nm. The raised source drain structures are fabricated by growing a selective epitaxial silicon layer in the source and drain regions of the MOSFET device after sidewall spacer creation and before HDD implant. The layers were grown in a low pressure LPCVD epitaxy reactor with a mixture of silane and dichlorosilane. A pre epitaxy process that eliminates the need for a pre epitaxy bake in hydrogen has been developed. In this study we have varied the thickness of this selective epitaxial silicon layer to investigate the effect of this parameter on device performance. Reducing the channel length of the devices has a detrimental effect on SCE and DIBL. In this paper we will show how short channel performance can be retrieved by adding the raised source drain structures, and how increasing the thickness of these structures improves these parameters further.
引用
收藏
页码:223 / 226
页数:4
相关论文
共 28 条
  • [21] Nanoscale SOI MOSFETs with electrically induced source/drain extension: Novel attributes and design considerations for suppressed short-channel effects
    Orouji, Ali A.
    Kumar, M. Jagadesh
    SUPERLATTICES AND MICROSTRUCTURES, 2006, 39 (05) : 395 - 405
  • [22] A Compact Model of Subthreshold Current With Source/Drain Depletion Effect for the Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs
    Xiao, Ying
    Zhang, Baili
    Lou, Haijun
    Zhang, Lining
    Lin, Xinnan
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (05) : 2176 - 2181
  • [23] A novel body effect reduction technique to recessed channel transistor featuring partially insulating layer under source and drain: Application to sub-50nm DRAM cell
    Park, Jong-Man
    Sohn, Si-Ok
    Park, Jung-Soo
    Han, Sang-Yeon
    Lee, Jun-Bum
    Kim, Wookje
    Jeon, Chang-Hoon
    Kim, Shin-Deuk
    Kim, Young-Pil
    Lee, Yong-Seok
    Yamada, Satoru
    Yang, Wouns
    Park, Donggun
    Lee, Won-Seong
    2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, : 903 - +
  • [24] Extreme Short-Channel Effect on RTS and Inverse Scaling Behavior: Source-Drain Implantation Effect in 25-nm NAND Flash Memory
    Kim, Taehoon
    Franklin, Nathan
    Srinivasan, Charan
    Kalavade, Pranav
    Goda, Akira
    IEEE ELECTRON DEVICE LETTERS, 2011, 32 (09) : 1185 - 1187
  • [25] Self-aligned Metallic Source and Drain Fin-on-Insulator FinFETs with Excellent Short Channel Effects Immunity down to 20 nm Gate Length
    Zhang, Qingzhu
    Li, Junjie
    Tu, Hailing
    Yi, Huaxiang
    Yan, Jiang
    Meng, Lingkuan
    Yao, Jiaxin
    Wang, Guilei
    Cao, Zhijun
    Li, Yudong
    Zhang, Zhaohao
    Wu, Zhenhua
    Wei, Feng
    Zhao, Hongbin
    Gao, Jiangfeng
    He, Xiaobin
    Jiang, Qifeng
    Xiong, Wenjuan
    Xiang, Jinjuan
    Zhou, Zhangyu
    Lu, Yihong
    Xu, Gaobo
    Luo, Kun
    Pan, Yu
    Xu, Renren
    Gu, Jie
    Hou, Chaozhao
    Li, Junfeng
    Wang, Wenwu
    2018 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC), 2018,
  • [26] Assessment of interface traps in In0.53Ga0.47As FinFET with gate-to-source/drain underlap for sub-14 nm technology node to impede short channel effect
    Pathak, Jay
    Darji, Anand
    IET CIRCUITS DEVICES & SYSTEMS, 2019, 13 (04) : 428 - 434
  • [27] Analysis of short-channel Schottky source/drain metal-oxide-semiconductor field-effect transistor on silicon-on-insulator substrate and demonstration of sub-50-nm n-type devices with metal gate
    Saitoh, W
    Itoh, A
    Yamagami, S
    Asada, M
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1999, 38 (11): : 6226 - 6231
  • [28] Analysis of short-channel Schottky source/drain metal-oxide-semiconductor field-effect transistor on silicon-on-insulator substrate and demonstration of sub-50-nm n-type devices with metal gate
    Saitoh, Wataru
    Itoh, Atsushi
    Yamagami, Shigeharu
    Asada, Masahiro
    Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 1999, 38 (11): : 6226 - 6231