Raised source/drain (RSD) for 50nm MOSFETs - Effect of epitaxy layer thickness on short channel effects.

被引：4

作者：

Waite, AM ^{[1
]}

Lloyd, NS ^{[1
]}

Ashburn, P ^{[1
]}

Evans, AGR ^{[1
]}

Ernst, T ^{[1
]}

Achard, H ^{[1
]}

Deleonibus, S ^{[1
]}

Wang, Y ^{[1
]}

Hemment, P ^{[1
]}

机构：

[1] Univ Southampton, Dept Elect & Comp Sci, Southampton SO17 1BJ, Hants, England

来源：

ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2003年

关键词：

D O I：

10.1109/ESSDERC.2003.1256854

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present raised source drain MOSFET devices with channel lengths down to 50nm. The raised source drain structures are fabricated by growing a selective epitaxial silicon layer in the source and drain regions of the MOSFET device after sidewall spacer creation and before HDD implant. The layers were grown in a low pressure LPCVD epitaxy reactor with a mixture of silane and dichlorosilane. A pre epitaxy process that eliminates the need for a pre epitaxy bake in hydrogen has been developed. In this study we have varied the thickness of this selective epitaxial silicon layer to investigate the effect of this parameter on device performance. Reducing the channel length of the devices has a detrimental effect on SCE and DIBL. In this paper we will show how short channel performance can be retrieved by adding the raised source drain structures, and how increasing the thickness of these structures improves these parameters further.

引用

页码：223 / 226

页数：4

共 28 条

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