A Power-Efficient CMOS Active Rectifier with Circuit Delay Compensation for Wireless Power Transfer Systems

In this paper, an active CMOS rectifier with new delay compensation technique for wireless power transmission system is proposed. In order to reduce the delays of the comparators employed in the proposed rectifier, a new low-power common-gate comparator is proposed which presents higher speed compared with the conventional counterpart. Moreover, a negative feedback loop changes the bulk voltage of PMOS transistors in the comparator to compensate the remaining turn-off delay of the circuit and its variation against all process, voltage, and temperature variations. Therefore, due to the reduction in the delay and consequently the reverse current of the active diodes, power conversion efficiency and voltage conversion ratio (VCR) of the proposed rectifier are increased considerably. Besides, since the feedback signal is applied to the bulk terminal of transistors in the comparator, it does not need any extra circuitry for generating the required offset current. The proposed circuit is simulated in a standard 0.13-A mu m CMOS technology. Post-layout simulation results show that, with +/- 1.2 V input amplitude, the proposed circuit presents a maximum efficiency of 86.7% with 200 a"broken vertical bar loading, a peak VCR of 97%, and a minimum voltage ripple of 6.5 mV with 2 ka"broken vertical bar loading.