A New Design of Reverse Converter for a Three-Moduli Set

被引:2
|
作者
Molahosseini, Amir Sabbagh [1 ]
Sezavar, Sara [2 ]
Navi, Keivan [2 ]
机构
[1] Islamic Azad Univ, Dept Comp Engn, Sci & Res Branch, Tehran, Iran
[2] Shahid Beheshti Univ, Dept Elect & Comp Engn, Tehran, Iran
关键词
TO-BINARY CONVERTER; NUMBER SYSTEM; RESIDUE; 2(N)-1; RNS; IMPLEMENTATION; 2(N+1)-1;
D O I
10.1109/ISPACS.2009.5383901
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The residue number system (RNS) is a non-weighted number system which can result in high-speed and low-power implementation of digital signal processing (DSP) computation algorithms. In this paper, an efficient design of the reverse converter for the new three-moduli set {2(n)-1, 2(n), 2(2n+1)-1} is presented. The reverse converter is achieved by an adder-based implementation of mixed-radix conversion (MRC) algorithm. The proposed converter has lower conversion delay and less hardware requirements than the other converters for four-moduli sets with similar dynamic range. Furthermore, the proposed reverse converter is faster than the reverse converter of the recently introduced three-moduli set {2(n-1), 2(n), 2(2n+1)-1}.
引用
收藏
页码:57 / +
页数:2
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