Low-Power Single-Transistor Voltage-Mode Third-Order All-pass Filter in 65-nm CMOS

被引：0

作者：

Elamien, M. B. ^{[1
]}

Maundy, B. J. ^{[1
]}

Belostotski, L. ^{[1
]}

Elwakil, A. S. ^{[1
,2
,3
]}

机构：

[1] Univ Calgary, Dept Elect & Comp Engn, Calgary, AB, Canada

[2] Univ Sharjah, Dept Elect & Comp Engn, Sharjah, U Arab Emirates

[3] Nile Univ, Nanoelect Integrated Syst Ctr NISC, Giza, Egypt

来源：

2020 IEEE 63RD INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2020年

关键词：

All-pass filter; CMOS TTD; third-order filters; TRUE-TIME-DELAY;

D O I：

10.1109/mwscas48704.2020.9184478

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This work proposes a new third-order wide-band all-pass filter (APF) circuit as a true time delay (TTD) element. The proposed APF is a voltage-mode circuit which only includes one transistor, one inductor, two resistors, and two capacitors. Post-layout simulation results in 65-nm CMOS process are used to validate the performance of the proposed circuit. The presented third-order CMOS APF achieves a group delay (GD) of 65.4 ps for about 12.7 GHz bandwidth while it consumes only 597 mu W. It also demonstrates a delay-bandwidth (DBW) of 0.83. Finally, the presented APF achieves an input-referred IP3 of 8.32 dBm and occupies an area of 148 mu m x 201 mu m.

引用

页码：1 / 4

页数：4

共 44 条

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