Electrical/optical high speed scalability link implementation

Increased demand for performance continues to drive higher chip internal clock frequencies and parallelism, as well as raise the demand for higher bandwidth and lower latencies. Today's copper digital communication links are limited by their loss characteristic which are dominated at high data rates by skin effects and dielectric loss. These physical links are typically used to interconnect multiple processor subsystems to build symmetric multi-processor (SMP) systems, as well as to connect input/output (1/0) subsystems across relative long distances. This paper describes the design challenges and solutions encountered during the design of a highly scalable SMP digital system with data rates of 3.2 GT/s (GigaTransfers per second) and higher. It contrasts the usage of copper and optical interconnect technology to achieve the overall system design goals from the perspective of link performance and physical design constraints.