POWER-DRIVEN MAPPING K-LUT-BASED FPGA CIRCUITS

被引：0

作者：

Bucur, I. ^{[1
]}

Cupcea, N. ^{[1
]}

Stefanescu, C. ^{[1
]}

Surpateanu, A. ^{[1
]}

机构：

[1] Univ Politehn Bucuresti, Dept Comp Sci & Engn, Bucharest, Romania

来源：

CAS: 2009 INTERNATIONAL SEMICONDUCTOR CONFERENCE, VOLS 1 AND 2, PROCEEDINGS | 2009年

关键词：

spurious switching power; K-feasible cones; optimum depth; optimal area and power;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper is presented a new approach for decreasing the spurious power consumption in K-LUT based FPGA implemented circuits. The approach is based on selective collapsing nodes in a direct acyclic graph (DAG) representing combinational or synchronous sequential circuits. It was used the simulation-based approach that estimates, using Monte Carlo experiment, the spurious switching activity of each net in the circuit. Traversing circuits in topological order, step by step best K-feasible cone are computed at the output of each node. Preserving the best depth of the circuits the mapping stage is done searching to minimize spurious switching power.

引用

页码：435 / 438

页数：4

共 50 条

[41] FPGA Delay-Oriented Process Mapping Algorithm of Xiangxi Minority Based on LUT
Xiao, Yun
Zeng, Wei
Zhang, Huang
MATHEMATICAL PROBLEMS IN ENGINEERING, 2022, 2022
[42] Power-aware technology mapping for LUT-Based FPGAs
Anderson, JH
Najm, FN
2002 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), PROCEEDINGS, 2002, : 211 - 218
[43] A Fast Simulator in FPGA for LUT-Based Combinational Logic Circuits of Arbitrary Topology for Evolutionary Algorithms
Cabrita, Daniel Mealha
Erig Lima, Carlos Raimundo
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2016, 25 (02)
[44] Mapping for Better Than Worst-Case Delays In LUT-Based FPGA Designs
Cong, Jason
Minkovich, Kirill
FPGA 2008: SIXTEENTH ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE GATE ARRAYS, 2008, : 56 - 64
[45] A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs
Legl, C
Wurth, B
Eckl, K
33RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 1996, 1996, : 730 - 733
[46] An ultrathin-barrier AlGaN/GaN heterostructure: a recess-free technology for the fabrication and integration of GaN-based power devices and power-driven circuits
Huang, Sen
Wang, Xinhua
Liu, Xinyu
Sun, Qian
Chen, Kevin J.
SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2021, 36 (04)
[47] An improved algorithm for performance optimal technology mapping with retiming in LUT-based FPGA design
Cong, J
Wu, C
INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1996, : 572 - 578
[48] ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping
Huang, JD
Jou, JY
Shen, WZ
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2000, 8 (04) : 392 - 400
[49] LUT-BASED FPGA TECHNOLOGY MAPPING UNDER ARBITRARY NET-DELAY MODELS
CONG, J
DING, YZ
GAO, T
CHEN, KC
COMPUTERS & GRAPHICS, 1994, 18 (04) : 507 - 516
[50] Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design
Cong, J
Hwang, YY
33RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 1996, 1996, : 726 - 729

← 1 2 3 4 5 →