Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers

被引：0

作者：

Su, Tiankai ^{[1
]}

Yasin, Atif ^{[1
]}

Yu, Cunxi ^{[1
,2
]}

Ciesielski, Maciej ^{[1
]}

机构：

[1] Univ Massachusetts, ECE Dept, Amherst, MA 01003 USA

[2] Ecole Polytech Fed Lausanne, LSI, Lausanne, Switzerland

来源：

2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2018年

基金：

美国国家科学基金会;

关键词：

Galois Field; Arithmetic circuits; Formal verification; Computer Algebra; Logic Debugging;

D O I：

10.1109/ISCAS.2018.8351397

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The paper presents a novel method to verify and debug gate-level arithmetic circuits implemented in Galois Field arithmetic. The method is based on forward reduction of the specification polynomials of the circuit in GF(2(m)) using GF(2) models of its logic gates. We define a forward variable order "FO >" and the rules of forward reduction that enable verification, bug detection, and automatic bug correction in the circuit. By analyzing the remainder generated by forward reduction, the method can determine whether the circuit is buggy, and finds the location and the type of the bug. The experiments performed on Mastrovito and Montgomery multipliers show that our debugging method is independent of the location of the bug(s) and the debugging time is comparable to the time needed to verify the bug-free circuit.

引用

页数：5

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