An SEU Hardened 65nm/4T-SRAM Cell for High Reliable Space Applications

被引：0
|
作者：
Zhang Wendi [1 ]
Pan Liyang [1 ]
机构：
[1] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China
来源：
PROCEEDINGS OF THE 2017 5TH INTERNATIONAL CONFERENCE ON FRONTIERS OF MANUFACTURING SCIENCE AND MEASURING TECHNOLOGY (FMSMT 2017) | 2017年 / 130卷
关键词：
SEU; High reliable space;
D O I：
暂无
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
A novel mono-stable 4T-SRAM cell is proposed in this paper. The cell is designed in 65nm LPCMOS process and simulated to find out the linear energy transfer threshold of SEU. T-CAD simulation results show that its LETth for data(1) is up to 41.6 MeV/mg/cm(2), almost the same as DICE, and the data error rate can be reduce to 1.2x10(-11)/bit. day with a particular duplication redundancy SRAM structure. The proposed 4T cell takes advantage of small cell size and solid anit-SEU ability, showing good potential to be used in SEU hardened SRAM.
引用
收藏
页码：635 / 638
页数：4
相关论文
共 50 条
  • [1] A Reliable and high performance Radiation Hardened Schmitt Trigger 12T SRAM cell for space applications
    Soni, Lokesh
    Pandey, Neeta
    AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2024, 176
  • [2] Radiation Tolerant SRAM Cell Design in 65nm Technology
    JianAn Wang
    Xue Wu
    Haonan Tian
    Lixiang Li
    Shuting Shi
    Li Chen
    Journal of Electronic Testing, 2021, 37 : 255 - 262
  • [3] An SRAM PUF With 2 Independent Bits/Cell in 65nm
    Shifman, Yizhak
    Miller, Avi
    Weizman, Yoav
    Fish, Alexander
    Shor, Joseph
    2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2019,
  • [4] Radiation Tolerant SRAM Cell Design in 65nm Technology
    Wang, JianAn
    Wu, Xue
    Tian, Haonan
    Li, Lixiang
    Shi, Shuting
    Chen, Li
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2021, 37 (02): : 255 - 262
  • [5] Area Compact 5T Portless SRAM cell for High Density Cache in 65nm CMOS
    Yadav, Jitendra Kumar
    Das, Pallavi
    Jain, Abhinav
    Grover, Anuj
    2015 19TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST (VDAT), 2015,
  • [6] Standby Power Reduction and SRAM Cell Optimization for 65nm Technology
    Lakshminarayanan, S.
    Joung, J.
    Narasimhan, G.
    Kapre, R.
    Slanina, M.
    Tung, J.
    Whately, M.
    Hou, C-L.
    Liao, W-J.
    Lin, S-C.
    Ma, P-G.
    Fan, C-W.
    Hsieh, M-C.
    Liu, F-C.
    Yeh, K-L.
    Tseng, W-C.
    Lu, S. W.
    ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2, 2009, : 471 - +
  • [7] 65NM SUB-THRESHOLD 11T-SRAM FOR ULTRA LOW VOLTAGE APPLICATIONS
    Moradi, Farshad
    Wisland, Dag T.
    Aunet, Snorre
    Mahmoodi, Hamid
    Cao, Tuan Vu
    IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2008, : 113 - +
  • [8] Statistical exploration of the dual supply voltage space of a 65nm PD/SOI CMOS SRAM cell
    Joshi, Rajiv
    Kanj, Rouwaida
    Nassif, Sani
    Plass, Donald
    Chan, Yuen
    Chuang, Ching-Te
    ESSDERC 2006: PROCEEDINGS OF THE 36TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2006, : 315 - +
  • [9] A 14T radiation hardened SRAM for space applications with high reliability
    Bai, Na
    Qin, Zhangyi
    Li, Li
    Xu, Yaohua
    Wang, Yi
    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2024, 52 (06) : 2956 - 2970
  • [10] SEU tolerance improvement in 22 nm UTBB FDSOI SRAM based on a simple 8T hardened cell
    Cai, C.
    Zhao, P. X.
    Xu, L. W.
    Liu, T. Q.
    Li, D. Q.
    Ke, L. Y.
    He, Z.
    Liu, J.
    MICROELECTRONICS RELIABILITY, 2019, 100
12345