Power Rail ESD Circuit Simulation and Verification

In order to advance the performance of the ESD circuit for the power rail protection, a kind of design scheme named GDNMOS (Gate Driven NMOS) is studied in this paper. NMOS, inverter and RC couple cell are the makeup in this scheme. Device simulation in a pre_Si phase will be an economical way. NMOS parameters are optimized in a device simulation way firstly. By discharge time study the RC-time is ascertained to differentiate ESD or not. And short delay is achieved by appropriate inverter design. This scheme with optimized parameters, not only the turn on speed is accelerated, but also better transparency is achieved. Turn on uniformity of the NMOS is also enhanced by this scheme. The design is verified in a 0.18um salicided CMOS process finally.