Power Rail ESD Circuit Simulation and Verification

被引：1
|
作者：
Li Zhiguo [1 ]
Yue Suge [1 ]
Sun Yongshu [1 ]
机构：
[1] Beijing Microelect Technol Inst, Beijing, Peoples R China
来源：
2009 IEEE INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC 2009) | 2009年
关键词：
ESD; GDNMOS; Simulation; TLP;
D O I：
10.1109/EDSSC.2009.5394179
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In order to advance the performance of the ESD circuit for the power rail protection, a kind of design scheme named GDNMOS (Gate Driven NMOS) is studied in this paper. NMOS, inverter and RC couple cell are the makeup in this scheme. Device simulation in a pre_Si phase will be an economical way. NMOS parameters are optimized in a device simulation way firstly. By discharge time study the RC-time is ascertained to differentiate ESD or not. And short delay is achieved by appropriate inverter design. This scheme with optimized parameters, not only the turn on speed is accelerated, but also better transparency is achieved. Turn on uniformity of the NMOS is also enhanced by this scheme. The design is verified in a 0.18um salicided CMOS process finally.
引用
收藏
页码：107 / 110
页数：4
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