Parasitics reduction for analog circuit simulation

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作者
Kahlert, M
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TM [电工技术]; TN [电子技术、通信技术];
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0808 ; 0809 ;
摘要
The modeling of interconnect lines using lumped elements results in large nets that in general can only be handled after a reduction of these parasitic elements. This paper presents an alternative to the Pade via Lanczos methods like SymPVL which allows for a direct error estimation by working in the time domain instead of approximating the transfer function. The proposed method uses a direct eigenvalue calculation which is performed with the Jacobi Davidson algorithm.
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页码:219 / 227
页数:9
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