Operational amplifiers (OpAmps) have found extensive applications in analog circuits and systems for communications, consumer electronics, controls and signal conversion. Two-stage OpAmps with frequency compensation are popular for driving capacitive loads while ensuring sufficient gain and stability. Frequency compensation techniques have been evolving over the last decades in distinct applications. In particular, power-and-area-efficent two-stage OpAmps capable of driving a wide-range capacitive load are demanded for low-dropout regulators (LDOs) or LCD-panel drivers. Capacitor multiplers (CMs) have emerged as one of the best solutions to implement such kind of OpAmps. This article reviews, for the first time, the state-of-the-art CMs for two-stage OpAmps before describing a novel embedded-CM technique, i.e., the CM as being part of the input stage of the OpAmp, effectively minimizing the physical size of the compensation capacitors while improving the slew-rate with no extra power consumption. Moreover, unlike the classical Miller compensation technique that can lead to an undesired right-half-plane (RHP) zero, a constructive left-half-plane (LHP) zero, is created, that can improve the phase margin (PM). Comparing with the state-of-the-art current-buffer and CM compensation topologies the proposed solution also features simpler circuitry. The technique can be further incorporated with a class-AB output stage to speed up the OpAmp's transient responses with low quiescent power. A descriptive design example capable of driving capacitive loads >= 50 pF is systematically optimized in a 0.35-mu m CMOS process. Finally, a few techniques are outlined which allow the combination of current-buffer-based Miller compensation with more sophisticated CMs, or a pole-zero pair (lead network), to further enhance the driving capability of two-stage OpAmps.
