Rapid Estimation of DSPs Utilization for Efficient High-Level Synthesis

被引：0

作者：

Aung, Yan Lin ^{[1
]}

Lam, Siew-Kei ^{[1
]}

Srikanthan, Thambipillai ^{[1
]}

机构：

[1] Nanyang Technol Univ, Sch Comp Engn, CHiPES Res Ctr, Singapore, Singapore

来源：

2015 IEEE INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING (DSP) | 2015年

关键词：

DSP blocks utilization; high-level estimation; high-level synthesis; DESIGNS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

High-level synthesis tools are increasingly adopted for designing complex applications on FPGAs. These tools necessitate fast and accurate estimation of FPGA resources in order to produce good design solutions while minimizing design time. Multiplication operations are very commonly found in signal processing, communication, video and image processing applications. In this paper, we present a rapid technique to estimate DSPs utilization for different types of multiplication operations during high-level synthesis. The proposed technique models the synthesis inferences and optimizations performed by state-of-the-art FPGA design tool in order to reliably estimate the number of DSPs and associated LUTs cost of multiplication operations.

引用

页码：1261 / 1265

页数：5

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